RPI ID: 2014-060-401

Innovation Summary:
This invention describes a memory architecture designed to operate effectively even when memory cells are defective or weak. The system identifies memory addresses associated with high error likelihood and applies customized handling, including virtual repairs, coding, and look-up mechanisms. It provides tiered error management that scales across memory devices, enabling robust operation without full hardware redundancy. The approach supports memory scaling below 20 nm by relaxing traditional requirements for perfect data retention. This error-tolerant method enhances the viability of next-generation non-volatile memories like STT-RAM.

Challenges / Opportunities:
As memory scales down in size, achieving uniform reliability across all cells becomes increasingly difficult. Traditional ECC (error correction code) schemes are often insufficient or too expensive in area and power. This invention enables graceful degradation of performance while maintaining overall system integrity. It opens up pathways to more energy-efficient, high-density memory systems for data centers and mobile platforms.

Key Benefits / Advantages:
✔ Enables sub-20nm memory scaling
✔ Minimal performance and power overhead
✔ Robust error correction without full redundancy

Applications:
• STT-RAM and emerging memory systems
• Embedded processors and IoT
• Fault-tolerant computing platforms

Keywords:
#memorydesign #errortolerance #ecc #sttram #scaling

Intellectual Property:
US Issued Patent 10,020,822 B2